Up until now, most data transferring between computer peripherals are completed through the communication between host bridges and host controllers, which are initialized and controlled by central processing units (CPUs) or micro controller units (MCUs). However, the conventional means adopted for transferring data not only causes the CPU/MCU to have a comparatively higher loading, but also might slow down the performance of the data accessing between computer peripherals.
Please refer to FIG. 1, which is a conceptual system view of prior arts. As seen in FIG. 1, both the host controllers 110, 120 are capable of directly memory access (DMA), that is, if there are data must be transfer from one external bus A to another external bus B, the host controller 110 will first move data from the corresponding external buses A to a local system memory 130 by way of a memory controller 125, and then the host controller 120 will be able to access the data registered in the local system memory 130 and transferring the same to the external bus B.
From the above description, since a host controller with DMA can move data between external bus and local system memory by itself, the CPU 140 only need to initialize host controllers 110, 120 and prepares some instructions for the same, and then the host controllers 110, 120 can starts to transfer data. When either the host controller 110 or the host controller 120 finishes all its scheduled jobs, it can inform the CPU 140 and wait for next jobs. By virtue of this, the loading of the CPU 140 can be reduced since the host controllers 110, 120 with DMA capability are able to access the local system memory 130 directly and by its own.
However, while there are data to be transfer from the external bus A to the external bus B using the system seen in FIG. 1, the CPU 140 must employ the host bridge 150 to prepare schedule for the host controller 110 of bus A to move data from bus A to a space in the local system memory 130 by way of the memory controller 125, and then the CPU 140 must also employ the host bridge 150 to prepare another schedule for the host controller 120 of bus B to move data from such space in the local system memory 130 to the bus B also by way of the memory controller 125.
Hence, it is noted that the above means of data transferring will waste some time to transfer data to and from the local system memory 130. Moreover, if the local system memory 130 is very busy, then the performance of the system including the CPU 140, the host bridge 150, the host controllers 110, 120, the memory 130, and the memory controller 125 as well as the peripherals coupled to the same will be slow down.
In view of the above description, an improved method for accessing data is disclosed, which is capable of increasing the efficiency of data access by reducing the time consumed by registering data in the system memory while transferring data between computer peripherals.